Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

ABSTRACT

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.

BACKGROUND

The present invention generally relates to fabrication methods andresulting structures for semiconductor devices, and more specifically,to fabrication methods and resulting structures for a novel field effecttransistor (FET) architecture configured to include a non-planar channelhaving vertically stacked nanosheets coupled to one another byfin-shaped bridge regions. This novel FET and non-planar channelarchitecture are identified herein as an X-FET device/architecture.

Traditional metal oxide semiconductor field effect transistor (MOSFET)fabrication techniques include process flows for constructing planarfield effect transistors (FETs). A planar FET includes a substrate (alsoreferred to as a silicon slab), a gate formed over the substrate, sourceand drain regions formed on opposite ends of the gate, and a channelregion near the surface of the substrate under the gate. The channelregion electrically connects the source region to the drain region whilethe gate controls the current in the channel. The gate voltage controlswhether the path from drain to source is an open circuit (“off”) or aresistive path (“on”).

In recent years, research has been devoted to the development ofnonplanar transistor architectures to achieve increased device density,greater power efficiency, and some increased performance over lateraldevices. For example, in a non-planar transistor architecture known as ananosheet-type field effect transistor (NSFET), the gate stack wrapsaround the full perimeter of each nanosheet. These nonplanararchitectures can provide for a fuller depletion in the channel regionwhen compared to some planar devices and can reduce short-channeleffects due to a steeper subthreshold swing (SS) and smaller draininduced barrier lowering (DIBL). The wrap-around gate structures and thesource/drain contacts used in an NSFET (sometimes referred to asgate-all-around (GAA) transistor) can also enable greater management ofleakage current and parasitic capacitance in the active regions, even asdrive currents increase.

SUMMARY

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a non-planar channel region having a first semiconductor layer,a second semiconductor layer, and a fin-shaped bridge layer between thefirst semiconductor layer and the second semiconductor layer. Formingthe non-planar channel region can include forming a nanosheet stack overa substrate, forming a trench by removing a portion of the nanosheetstack, and forming a third semiconductor layer in the trench. Outersurfaces of the first semiconductor layer, the second semiconductorlayer, and the fin-shaped bridge region define an effective channelwidth of the non-planar channel region.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a semiconductor layer on a substrate. A stack of alternatingoxide layers and nitride layers are formed adjacent to the semiconductorlayer and the oxide layers are removed to expose a sidewall of thesemiconductor layer. The method further includes recessing the exposedsidewall of the semiconductor layer to define a vertical portion and oneor more horizontal portions of the semiconductor layer.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a nanosheet stack over a substrate. The nanosheet stack includesa first semiconductor layer and a second semiconductor layer. The secondsemiconductor layer includes a first material. The method furtherincludes recessing a sidewall of the second semiconductor layer andannealing at a temperature operable to uniformly diffuse the firstmaterial through the first semiconductor layer and the secondsemiconductor layer.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a stack of alternating semiconductor layers and dopedsemiconductor layers over a substrate. The doped semiconductor layersincludes a dopant. The method further includes recessing a sidewall ofthe doped semiconductor layers and annealing at a temperature operableto uniformly diffuse the dopant through the semiconductor layers and thedoped semiconductor layers.

Embodiments of the invention are directed to a semiconductor structure.A non-limiting example of the structure includes a channel region over asubstrate. The channel region includes a vertical fin and one or morevertically stacked nanosheets. Each of the one or more verticallystacked nanosheets extend from a sidewall of the vertical fin. A gate isformed over the channel region. The gate is in contact with a sidewallof the vertical fin and a top and bottom surface of each of the one ormore vertically stacked nanosheets.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a nanosheet stack over a substrate. The nanosheet stack includesone or more first semiconductor layers and one or more first sacrificiallayers. A trench is formed by removing a portion of the one or morefirst semiconductor layers and the one or more first sacrificial layers.The trench exposes a surface of a bottommost sacrificial layer of theone or more first sacrificial layers. The method further includesfilling the trench with one or more second semiconductor layers and oneor more second sacrificial layers such that each of the one or moresecond semiconductor layers is in contact with a sidewall of one of theone or more first semiconductor layers.

Embodiments of the invention are directed to a method of forming asemiconductor device. A non-limiting example of the method includesforming a first channel region over a substrate. The first channelregion includes a first vertical fin and a first nanosheet extendingfrom a sidewall of the first vertical fin. A second channel region isformed over the first channel region. The second channel region includesa second vertical fin and a second nanosheet extending from a sidewallof the second vertical fin. A gate is formed over the first channelregion and the second channel region. The gate is in contact with atopmost surface of the first channel region and a bottommost surface ofthe second channel region.

Embodiments of the invention are directed to a semiconductor structure.A non-limiting example of the structure includes a first channel regionover a substrate. The first channel region includes a first vertical finand a first nanosheet extending from a sidewall of the first verticalfin. The structure further includes a second channel region over thefirst channel region. The second channel region includes a secondvertical fin and a second nanosheet extending from a sidewall of thesecond vertical fin. A gate wraps around the first channel region andthe second channel region. The gate is in contact with a topmost surfaceof the first channel region and a bottommost surface of the secondchannel region.

Additional technical features and benefits are realized through thetechniques of the present invention. Embodiments and aspects of theinvention are described in detail herein and are considered a part ofthe claimed subject matter. For a better understanding, refer to thedetailed description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe embodiments of the invention are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1A illustrates an effective channel width for an X-FET architectureaccording to one or more embodiments of the invention;

FIG. 1B illustrates an effective channel width for a gate-all-around(GAA) X-FET architecture according to one or more embodiments of theinvention;

FIGS. 2A-15B depict cross-sectional views of an X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 2A depicts a top-down view of the X-FET semiconductor structureafter processing operations according to one or more embodiments of theinvention;

FIG. 2B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 2C depicts a cross-sectional view of the X-FET semiconductorstructure of FIG. 2A after processing operations according to one ormore embodiments of the invention;

FIG. 3A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 3B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 4A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 4B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 5A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 5B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 6A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 6B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 7A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 7B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 8A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 8B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 9A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 9B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 10A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 10B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 11A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 11B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 12A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 12B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 13A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 13B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 14A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 14B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 15A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 15B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIGS. 16A-19C depict cross-sectional views of a GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 16A depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 16B depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 17A depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 17B depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 18A depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 18B depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 19A depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 19B depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 19C depicts a cross-sectional view of the GAA X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIGS. 20-28 depict cross-sectional views of an X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 20 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 21 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 22 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 23 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 24 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 25 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 26 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 27 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 28 depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIGS. 29A-31B depict cross-sectional views of an X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 29A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 29B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 30A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 30B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 31A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 31B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIGS. 32A-35B depict cross-sectional views of an X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 32A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 32B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 33A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 33B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 34A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 34B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 35A depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 35B depicts a cross-sectional view of the X-FET semiconductorstructure after processing operations according to one or moreembodiments of the invention;

FIG. 36 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention;

FIG. 37 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention;

FIG. 38 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention;

FIG. 39 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention;

FIG. 40 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention; and

FIG. 41 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention.

The diagrams depicted herein are illustrative. There can be manyvariations to the diagram or the operations described therein withoutdeparting from the spirit of the invention. For instance, the actionscan be performed in a differing order or actions can be added, deletedor modified.

In the accompanying figures and following detailed description of thedescribed embodiments of the invention, the various elements illustratedin the figures are provided with two or three-digit reference numbers.With minor exceptions, the leftmost digit(s) of each reference numbercorrespond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

It is understood in advance that although example embodiments of theinvention are described in connection with a particular transistorarchitecture, embodiments of the invention are not limited to theparticular transistor architectures or materials described in thisspecification. Rather, embodiments of the present invention are capableof being implemented in conjunction with any other type of transistorarchitecture or materials now known or later developed.

For the sake of brevity, conventional techniques related tosemiconductor device and integrated circuit (IC) fabrication may or maynot be described in detail herein. Moreover, the various tasks andprocess steps described herein can be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein. In particular, varioussteps in the manufacture of semiconductor devices andsemiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

Turning now to an overview of technologies that are more specificallyrelevant to aspects of the present invention, ametal-oxide-semiconductor field-effect transistor (MOSFET) is used foramplifying or switching electronic signals. The MOSFET has a source, adrain, and a metal oxide gate electrode. The metal gate portion of themetal oxide gate electrode is electrically insulated from the mainsemiconductor n-channel or p-channel by the oxide portion of the metaloxide gate electrode. The oxide portion of the gate electrode can beimplemented as a thin layer of insulating material, for example, silicondioxide or glass, which makes the input resistance of the MOSFETrelatively high. The gate voltage controls whether the current path fromthe source to the drain is an open circuit (“off”) or a resistive path(“on”). N-type field effect transistors (NFET) and p-type field effecttransistors (PFET) are two types of complementary MOSFETs. The NFETincludes n-doped source and drain junctions and uses electrons as thecurrent carriers. The PFET includes p-doped source and drain junctionsand uses holes as the current carriers. Complementary metal oxidesemiconductor (CMOS) is a technology that uses complementary andsymmetrical pairs of p-type and n-type MOSFETs to implement logicfunctions.

As previously noted herein, traditional MOSFET fabrication techniquesinclude process flows for constructing planar transistor architecturesand nonplanar transistor architectures. One goal for designing nonplanartransistor architectures is to increase the effective channel width(W_(eff)) for a given device footprint within the constraints of thecurrent processing node (e.g., the width of the device processingwindow, sometimes denoted RX). The effective channel width of atransistor can be defined as the total width of the transistor's channelin contact with the transistor's gate. Hence the larger the effectivechannel width, the more drive current the transistor will be able todeliver. For comparison, the effective channel width for a 50 nm wideplanar transistor is simply the width of the gate (e.g., 50 nm). NSFETswere developed to increase the effective channel width for a givenfootprint while improving the electrostatic control of the channel aswell. Continuing the above example, a 50 nm high three-nanosheet stackhaving a nanosheet width of 15 nm and a nanosheet thickness of 5 nmprovides an effective channel width of 120 nm. By increasing theeffective channel width, a larger effective depletion region in thechannel is achieved enabling the device to provide higher drive currentat a given gate voltage. This in turn can increase device performanceand can enable further device scaling. Consequently, there issignificant interest in further improving the effective channel widthfor a given device footprint.

There are challenges, however, associated with increasing the effectivechannel width of a transistor beyond the 20 nm node. For example,nanosheet-based SRAM devices require narrow sheet devices (in the 10-15nm range) due to cell scaling requirements. At these dimensions theeffective channel width of a NSFET is significantly reduced and thedevice architecture loses some performance benefits in terms of drivecurrent capabilities.

In theory, the effective channel width of a NSFET device could beincreased by increasing the sheet width or increasing the number ofsheets. Each of these approaches has its disadvantages. For example,process limitations put practical limits on how wide the nanosheetdevice can be, preventing arbitrarily large increases in sheet width.Conventional processes are currently constrained by an upper limit ofabout 100 nm for the sheet width. Moreover, increasing the sheet widthdirectly means increasing the foot print of the device. In other words,each transistor takes more room on the wafer, which is not ideal forscaling.

Increasing the number of sheets significantly increases the effectivechannel width for a given device foot print. Based on simulations,however, the optimal number of sheets for a NSFET is 3 (this followsfrom a co-optimization of the drive current and parasitic capacitance).Adding a fourth sheet on top of the stack is possible, but theintegration scheme complicates the fabrication process, due in part toaspect ratio considerations. Moreover, the device might actually performworse than a 3-sheet device due to the corresponding increase inparasitic capacitance.

Turning now to an overview of aspects of the present invention,embodiments of the invention address the above-described shortcomings ofthe prior art by providing fabrication methods and resulting structuresfor a new transistor architecture described herein as an X-type fieldeffect transistor (X-FET). Described broadly, the X-FET architectureherein includes a non-planar channel having a set of vertically stackednanosheets coupled to one another by fin-shaped bridge regions. In someembodiments of the invention, the X-FET is combined with a gate allaround (GAA) process to further increase the effective channel width andimprove the device electrostatics. The resulting hybrid architecturesshow a significant effective channel width (W_(eff)) boost over 3-sheetNSFETs for any given RX width (at the same device footprint and withoutneeding to add additional nanosheets to the stack). The X-FET and GAAX-FET architectures also outperform 4-sheet NSFETs when RX is less than15 nm and 25 nm, respectively, while avoiding the increased fabricationcomplexities associated with nanosheet stacks having four or morenanosheets. Advantageously, the gate length is maintained similar toNSFETs. Consequently, X-FETs and GAA X-FETs provide the sameelectrostatic benefits as NSFETs, allowing very short gate lengths,while the increased effective channel widths provide higher drivecurrents (ON currents). FIGS. 1A and 1B illustrate the increases inW_(eff) available when using the X-FET (FIG. 1A) and the GAA X-FET (FIG.1B) architectures described herein.

Turning now to a more detailed description of aspects of the presentinvention, FIGS. 2A-15B depict various views of an “X-FET” semiconductorstructure 200 that result from performing fabrication operationsaccording to one or more embodiments of the invention.

For ease of illustration, FIG. 2A depicts a top-down view of the “X-FET”semiconductor structure 200 that illustrates the three cross-sectionalviews used in the following discussion. The “X-FET” type semiconductorstructure 200 includes a fin having a fin center and fin edges. The“X-FET” semiconductor structure 200 further includes a gate formed overa channel region of the fin. As depicted in FIG. 2A, the cross-fin view“X” is taken along a centerline of the gate. The cross-gate view “Y” istaken along the fin center. The cross-gate view “Z” is taken along thefin edge.

As depicted in FIGS. 2B and 2C, a partially fabricated semiconductordevice can include a first sacrificial layer 202 formed over a substrate204. The first sacrificial layer 202 can be made of any suitablesacrificial material, such as, for example, silicon germanium. In someembodiments of the invention, the germanium concentration in the firstsacrificial layer 202 is selected to ensure etch selectivity against anysilicon, silicon germanium or germanium layers in the subsequentlyformed gate stack. In other words, the first sacrificial layer 202 canbe etched selective to any silicon, silicon germanium or germanium inthe subsequently formed gate stack. In some embodiments of theinvention, the germanium concentration in the first sacrificial layer202 is at least 30 percent higher than the germanium concentration thanany other silicon germanium layers in the stack. In some embodiments ofthe invention, the first sacrificial layer 202 can include a germaniumconcentration of 45 to 70 percent, for example 50 percent, althoughother germanium concentrations are within the contemplated scope of theinvention.

The first sacrificial layer 202 can have a wide range of thickness suchas, for example, from 5 nm to 25 nm or more. In some embodiments of theinvention, the first sacrificial layer 202 is formed to a height ofabout 10 nm, although other thicknesses are within the contemplatedscope of the invention. The first sacrificial layer 202 can be formed bya variety of methods, such as, for example, chemical vapor deposition(CVD), plasma-enhanced CVD (PECVD), ultrahigh vacuum chemical vapordeposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD),metalorganic chemical vapor deposition (MOCVD), low-pressure chemicalvapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), andmolecular beam epitaxy (MBE). In some embodiments of the invention, thefirst sacrificial layer 202 can be epitaxially grown from gaseous orliquid precursors. Epitaxial semiconductor materials can be grown usingvapor-phase epitaxy (VPE), MBE, liquid-phase epitaxy (LPE), or othersuitable processes.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases are controlled and the systemparameters are set so that the depositing atoms arrive at the depositionsurface of the semiconductor substrate with sufficient energy to moveabout on the surface such that the depositing atoms orient themselves tothe crystal arrangement of the atoms of the deposition surface.Therefore, an epitaxially grown semiconductor material has substantiallythe same crystalline characteristics as the deposition surface on whichthe epitaxially grown material is formed. For example, an epitaxiallygrown semiconductor material deposited on a {100} orientated crystallinesurface will take on a {100} orientation. In some embodiments of theinvention, epitaxial growth and/or deposition processes are selective toforming on semiconductor surface, and generally do not deposit materialon other exposed surfaces, such as silicon dioxide or silicon nitridesurfaces.

The substrate 204 can be made of any suitable substrate material, suchas, for example, monocrystalline Si, silicon germanium (Silicongermanium), III-V compound semiconductor, II-VI compound semiconductor,or semiconductor-on-insulator (SOI). In some embodiments of theinvention, the substrate 204 can be a silicon substrate. In someembodiments of the invention, the substrate 204 includes a buried oxidelayer (not depicted). The buried oxide layer can be made of any suitabledielectric material, such as, for example, a silicon oxide. In someembodiments of the invention, the buried oxide layer is formed to athickness of about 145 nm, although other thicknesses are within thecontemplated scope of the invention. The semiconductor structure 200 canbe electrically isolated from other regions of the substrate 204 by ashallow trench isolation region (see FIG. 7A).

In some embodiments of the invention, a stack of one or moresemiconductor layers 206 alternating with one or more sacrificial layers208 is formed over the first sacrificial layer 202. The stack can beformed such that the topmost and bottommost layers of the stack are thesacrificial layers 208. While depicted as a stack having threesemiconductor layers 206 alternating with four sacrificial layers 208for ease of illustration, it is understood that the stack can includeany number of semiconductor layers 206 alternating with a correspondingnumber of sacrificial layers 208. For example, the stack can include twosemiconductor layers 206 alternating with three sacrificial layers 208.In the final transistor structure, the semiconductor layers 206 willfunction as the channel regions, and the sacrificial layers 208 will bereplaced with a portion of the transistor gate structure that wrapsaround the semiconductor/channel layers 206.

Each of the semiconductor layers 206 can have a height ranging from 4 nmto 20 nm, for example, from 7 nm to 10 nm. In some embodiments of theinvention, the semiconductor layers 206 have a height of about 9 nm. Thesemiconductor layers 206 can be made of any suitable semiconductorchannel material, such as, for example, monocrystalline Si, III-Vcompound semiconductor, or II-VI compound semiconductor. In someembodiments of the invention, the semiconductor layers 206 are made ofsilicon.

Each of the sacrificial layers 208 can have a height ranging from 4 nmto 20 nm, for example, from 8 nm to 15 nm. In some embodiments of theinvention, the sacrificial layers 208 have a height of about 8 nm. Insome embodiments of the invention, the sacrificial layers 208 are madeof silicon germanium. In some embodiments of the invention, thesacrificial layers 208 include a germanium concentration of 15 to 35percent, for example 25 percent, although other germanium concentrationsare within the contemplated scope of the invention.

The semiconductor layers 206 and the sacrificial layers 208 can beformed by a variety of methods, such as, for example, UHVCVD, RTCVD,MOCVD, LPCVD, LRPCVD, and MBE. In some embodiments of the invention, thesemiconductor layers 206 and the sacrificial layers 208 are epitaxiallygrown from gaseous or liquid precursors. Epitaxial semiconductormaterials can be grown using VPE, MBE, LPE, or other suitable processes.Epitaxial silicon and silicon germanium can be doped during deposition(in-situ doped) by adding n-type dopants (e.g., P or As) or p-typedopants (e.g., Ga, B, BF₂, or Al). The dopant concentration in the dopedregions can range from 1×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³, or between 1×10²⁰cm⁻³ and 1×10²¹ cm⁻³.

In some embodiments of the invention, the gas source for the depositionof epitaxial semiconductor material includes a silicon containing gassource, a germanium containing gas source, or a combination thereof. Forexample, an epitaxial Si layer can be deposited from a silicon gassource that is selected from the group consisting of silane, disilane,trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane,dichlorosilane, trichlorosilane, methylsilane, dimethylsilane,ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane andcombinations thereof. An epitaxial germanium layer can be deposited froma germanium gas source that is selected from the group consisting ofgermane, digermane, halogermane, dichlorogermane, trichlorogermane,tetrachlorogermane and combinations thereof. An epitaxial silicongermanium alloy layer can be formed utilizing a combination of such gassources. Carrier gases like hydrogen, nitrogen, helium and argon can beused. In some embodiments of the invention, the doped regions includesilicon. In some embodiments of the invention, the doped regions includecarbon doped silicon (Si:C). This Si:C layer can be grown in the samechamber used for other epitaxy steps or in a dedicated Si:C epitaxychamber. The Si:C can include carbon in the range of about 0.2 percentto about 3.0 percent.

FIGS. 3A and 3B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 3A and 3B, a hardmask 302 can be formed on the topmost layer of the sacrificial layers208. In some embodiments of the invention, the hard mask 302 includes anitride, such as silicon nitride. In some embodiments of the invention,the hard mask 302 is formed to a thickness of 40 nm, although otherthicknesses are within the contemplated scope of the invention. In someembodiments of the invention, a second hard mask (not depicted) can beformed on the hard mask 302, to form a bilayer hard mask. In someembodiments of the invention, the second hard mask includes an oxide,such as, for example, silicon dioxide.

In some embodiments of the invention, portions of the hard mask 302 areremoved (e.g., patterned) and the stack of semiconductor layers 206 andsacrificial layers 208 are patterned selective to the hard mask 302. Asillustrated in FIG. 3A, portions of the semiconductor layers 206 andsacrificial layers 208 that are not covered by the patterned hard mask302 can be removed using a wet etch, a dry etch, or a combination ofsequential wet and/or dry etches. In this manner, the semiconductorlayers 206 and sacrificial layers 208 can be patterned to expose one ormore surfaces of the substrate 204. In some embodiments of theinvention, the patterning process can result in a recessing of thesubstrate 104. In some embodiments of the invention, the stack ispatterned into one or more fins having a width ranging from 10 to 50 nm,although other widths are within the contemplated scope of theinvention. For ease of illustration, the stack is depicted as beingpatterned to form two fins. It is understood, however, that the stack bepatterned into any number of parallel fins.

In some embodiments of the invention, a shallow trench isolation (STI)304 is formed over the substrate 204 to electrically isolate the one ormore semiconductor fins. The STI 304 can be any suitable dielectricmaterial, such as, for example, a silicon oxide, and can be formed usingany suitable process. The STI 304 can be formed using, for example, CVD,flowable CVD (FCVD) plasma-enhanced CVD (PECVD), UHVCVD, RTCVD, MOCVD,LPCVD, LRPCVD, ALD, physical vapor deposition (PVD), high-density plasma(HDP), chemical solution deposition, spin-on dielectrics, or other likeprocesses. In some embodiments of the present invention, the STI 304 isoverfilled and then recessed using, for example, a chemical-mechanicalplanarization (CMP) process.

FIGS. 4A and 4B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 4A and 4B, thehard mask 302 can be stripped using, for example, a wet etch, a dryetch, or a combination of sequential wet and/or dry etches. In thismanner, sidewalls of the STI 304 can be exposed.

In some embodiments of the invention, fin spacers 402 are formed overthe topmost sacrificial layer of the sacrificial layers 208 and betweenthe exposed sidewalls of the STI 304. In some embodiments of theinvention, the fin spacers 402 are formed using conformal depositionprocess such as CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD,PVD, chemical solution deposition, or other like processes incombination with a wet or dry etch process. For example, spacer materialcan be conformally deposited over the semiconductor structure 200 andselectively removed using a RIE to form the fin spacers 402. The finspacers 402 can be made of any suitable material, such as, for example,a low-k dielectric, a nitride, silicon nitride, silicon oxide, SiON,SiC, SiOCN, or SiBCN. In some embodiments of the invention, the finspacers 402 include silicon nitride. The fin spacers 402 can be formedto a thickness of about 5 to 10 nm, for example 5 nm, although otherthicknesses are within the contemplated scope of the invention.

FIGS. 5A and 5B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 5A and 5B,portions of the semiconductor layers 206 and sacrificial layers 208 thatare not covered by the fin spacers 402 can be removed using a wet etch,a dry etch, or a combination of sequential wet and/or dry etches.

In some embodiments of the invention, these portions are removed using areactive ion etch (ME). In this manner, the semiconductor layers 206 andsacrificial layers 208 can be patterned to form a trench 502 exposingone or more surfaces of the first sacrificial layer 202. In someembodiments of the invention, the patterning process can result in arecessing of the first sacrificial layer 202. In some embodiments of theinvention, the semiconductor layers 206 and sacrificial layers 208 arepatterned into nanosheets having a width of 5 nm, although other widthsare within the contemplated scope of the invention.

FIGS. 6A and 6B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 6A and 6B, asemiconductor layer 602 is formed within the trench 502. In someembodiments of the invention, the semiconductor layer 602 is a bottom-uptrench epitaxy.

The semiconductor layer 602 can be formed by a variety of methods. Insome embodiments of the invention, epitaxial semiconductor materials canbe grown in the trench 502 using VPE, MBE, LPE, or other suitableprocesses. The semiconductor layer 602 can be made of any suitablesemiconductor channel material, such as, for example, monocrystallineSi, III-V compound semiconductor, or II-VI compound semiconductor. Insome embodiments of the invention, the semiconductor layer 602 is madeof a same material as the semiconductor layers 206, such as, forexample, silicon.

FIGS. 7A and 7B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 7A and 7B, the finspacers 402 can be filled in with additional material to form, orreplaced by, a hard mask 702.

The hard mask 702 can be formed using a CVD, PECVD, UHVCVD, RTCVD,MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or otherlike process. For example, dielectric material can be conformallydeposited over the semiconductor structure 200. The hard mask 702 can bemade of any suitable material, such as, for example, a low-k dielectric,a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN.In some embodiments of the invention, the hard mask 702 includes siliconnitride. The hard mask 702 can be formed to a thickness of about 5 to 50nm, for example 10 nm, although other thicknesses are within thecontemplated scope of the invention.

In some embodiments of the invention, the STI 304 is recessed below asurface of the first sacrificial layer 202. In this manner, the STI 304electrically isolates one or more nanosheets stacks. The STI 304 can berecessed using, for example, chemical oxide removal (COR) or ahydrofluoric acid (HF) wet etch. In some embodiments of the invention,the STI 304 is recessed selective to the hard mask 702.

FIGS. 8A and 8B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 8A and 8B, thehard mask 702 can be removed using, for example, a wet etch, a dry etch,or a combination of sequential wet and/or dry etches.

In some embodiments of the invention, a dielectric liner 802 is formedover the semiconductor structure 200. In some embodiments of theinvention, the dielectric liner 802 is formed using a conformaldeposition process such CVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD,ALD, PVD, chemical solution deposition, or other like process. Forexample, dielectric material can be conformally deposited over thesemiconductor structure 200. The dielectric liner 802 can be made of anysuitable material, such as, for example, a low-k dielectric, a nitride,silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In someembodiments of the invention, the dielectric liner 802 is a siliconoxide. The dielectric liner 802 can be formed to a thickness of about0.2 to 10 nm, for example 3 nm, although other thicknesses are withinthe contemplated scope of the invention.

In some embodiments of the invention, a sacrificial gate 804 is formedover the dielectric liner 802. The sacrificial gate 804 can be made ofany suitable material, such as, for example, amorphous silicon orpolysilicon. The sacrificial gate 804 can be formed using any knownmethod for patterning a sacrificial gate, such as, for example, apolysilicon fill and a wet etch, a dry etch, or a combination ofsequential wet and/or dry etches.

In some embodiments of the invention, a hard mask 806 (also known as agate hard mask) is formed on the sacrificial gate 804. The hard mask 806can be made of any suitable material, such as, for example, a siliconnitride. In some embodiments of the invention, a second hard mask 808 isformed on the hard mask 806, to form a bilayer hard mask. The secondhard mask 808 can include an oxide, such as, for example, a siliconoxide. In some embodiments of the invention, the sacrificial gate 804 isformed by patterning the hard masks 806 and 808 and removing uncoveredportions of the sacrificial gate 808 with a RIE.

FIGS. 9A and 9B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIG. 9B, portions of thedielectric liner 802 can be removed to expose a surface of the nanosheetstack(s) (e.g., the semiconductor layer 602). The dielectric liner 802can be removed using a wet or dry etch. In some embodiments of theinvention, the dielectric liner 802 is removed using an oxide strippingprocess.

As illustrated in FIGS. 9A and 9B, the first sacrificial layer 202 canbe removed selective to the sacrificial layers 208. The firstsacrificial layer 202 can be removed using any suitable process capableof removing a germanium layer selective to a lower concentrationgermanium layer. Example processes known to provide this etchselectivity include HC1 vapor phase chemistries and chlorine trifluoride(ClF₃) etches.

In some embodiments of the invention, spacer material 902 is formed overthe semiconductor structure 200. In some embodiments of the invention,for example, those having a first sacrificial layer 202 that issubsequently removed, the spacer material 902 is also formed within thecavity left by the removal of the first sacrificial layer 202. In thismanner, the spacer material 902 can replace the first sacrificial layer202 (if present). Replacing the first sacrificial layer 202 in this wayprovides for a bottom isolation between the nanosheet stacks and thesubstrate 204.

In some embodiments of the invention, the spacer material 902 is formedusing a conformal deposition process such as CVD, PECVD, UHVCVD, RTCVD,MOCVD, LPCVD, LRPCVD, ALD, PVD, chemical solution deposition, or otherlike process. For example, spacer material 902 can be conformallydeposited over the semiconductor structure 200. The spacer material 902can be made of any suitable material, such as, for example, a low-kdielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN,or SiBCN. In some embodiments of the invention, the spacer material 902includes SiBCN. The spacer material 902 can be formed or deposited to athickness of about 5 to 15 nm, although other thicknesses are within thecontemplated scope of the invention.

FIGS. 10A and 10B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 10A and 10B,portions of the spacer material 902 can be etched or otherwise patternedto form spacers 1002 (also known as sidewall spacers or gate spacers) onsidewalls of the sacrificial gate 804. The spacer material 902 can bepatterned using, for example, a wet etch or a dry etch. In someembodiments of the invention, the spacer material is selectively removedusing a RIE to form the side walls spacers 1002. In this manner, asurface of the nanosheet stack is exposed. In some embodiments of theinvention, exposed portions of the nanosheet stack (e.g., thesemiconductor layer 602 and the sacrificial layers 208) are removedselective to the spacer material 902 and/or the first sacrificial layer202.

FIGS. 11A and 11B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 11A and 11B, thesacrificial layers 208 are recessed and replaced with inner spacers1102. The sacrificial layers 208 can be recessed using a wet etch or adry etch. In some embodiments of the invention, the sacrificial layers208 are recessed selective to the semiconductor layers 206. For example,sacrificial layers 208 made of silicon germanium can be etched selectiveto semiconductor layers 206 made of silicon using a wet hydrophosphoricacid-based etchant or dry HCl or ClF₃ gas etchant. In some embodimentsof the invention, the sacrificial layers 208 are recessed to a depthselected such that the thickness of the inner spacers 1102 is the sameas the thickness of the spacers 1002.

In some embodiments of the invention, the inner spacers 1102 are formedby a conformal deposition (e.g., CVD or ALD) to plug the recesses formedin the sacrificial layers 208, followed by an etch back process toremove any excessive material. The inner spacers 1102 can be made of anysuitable material, such as, for example, a low-k dielectric, a nitride,silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN.

FIGS. 12A and 12B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 12A and 12B,source/drain (S/D) regions 1202 can be formed on a surface of the bottomisolation layer 902 and on opposite ends of each nanosheet stack. Insome embodiments of the invention, the S/D regions 1202 are epitaxiallygrown from the exposed ends of the fin/nanosheet stack (i.e., thesemiconductor layers 206).

The S/D regions 1202 can be epitaxially formed by a variety of methods,such as, for example, in-situ doped epitaxy, doped following theepitaxy, or by implantation and plasma doping. In some embodiments ofthe invention, epitaxial regions are epitaxially grown over a surface ofthe substrate 204. The S/D regions 1202 can be epitaxial semiconductormaterials grown from gaseous or liquid precursors, as describedpreviously herein. The S/D regions 1202 can be doped with n-type dopants(e.g., phosphorus or arsenic) or p-type dopants (e.g., boron orgallium). The dopant concentration in the S/D regions 1202 can rangefrom 1×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³, or between 1×10²⁰ cm⁻³ and 1×10²¹ cm⁻³.

FIGS. 13A and 13B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 13A and 13B, adielectric layer 1302 is formed over the S/D regions 1202 and betweenthe spacers 1002. The dielectric layer 1302 can be formed using, forexample, a CVD, FCVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD,PVD, chemical solution deposition, or other like process. The dielectriclayer 1302 can be made of any suitable material, such as, for example, alow-k dielectric, a nitride, silicon nitride, silicon oxide, SiON, SiC,SiOCN, or SiBCN. In some embodiments of the invention, the dielectriclayer 1302 is an oxide, such as silicon oxide.

In some embodiments of the present invention, the dielectric layer 1302is overfilled and then planarized to a top surface of the sacrificialgate 804 using, for example, a CMP process. In some embodiments of theinvention, the hard mask 806 and the second hard mask 808 are removedduring the CMP process.

FIGS. 14A and 14B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 14A and 14B, thesacrificial gate 804, the dielectric liner 802, and the sacrificiallayers 208 can be removed and replaced by a conductive gate 1402 duringa replacement metal gate (RMG) process. The sacrificial gate 804, thedielectric liner 802, and the sacrificial layers 208 can be removedusing known RMG processes. In some embodiments of the invention, thesacrificial gate 804 is removed using an amorphous silicon orpolysilicon pull. In some embodiments of the invention, the dielectricliner 802 is removed using an oxide etch.

In some embodiments of the invention, the sacrificial layers 208 areremoved selective to the semiconductor layers 206 and/or thesemiconductor layer 602. The sacrificial layers 208 can be removed usinga wet etch or a dry etch. In some embodiments of the invention,sacrificial layers 208 made of silicon germanium can be removedselective to semiconductor layers 206 and 602 made of silicon using awet hydrophosphoric acid-based etchant or dry HCl or ClF₃ gas etchant.In some embodiments of the invention, the sacrificial layers 208 areremoved prior to forming the conductive gate 1402.

The conductive gate 1402 can be a high-k metal gate (HKMG) formed using,for example, known RMG processes. In some embodiments of the invention,the conductive gate 1402 is a replacement metal gate stack formedbetween the spacers 1002. The replacement metal gate stack can include ahigh-k dielectric material, a work function metal stack, and a bulk gatematerial.

In some embodiments of the invention, the high-k dielectric film (notdepicted) is formed over an exposed surface of the nanosheet stack. Thehigh-k dielectric film can be made of, for example, silicon oxide,silicon nitride, silicon oxynitride, boron nitride, high-k materials, orany combination of these materials. Examples of high-k materials includebut are not limited to metal oxides such as hafnium oxide, hafniumsilicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, zirconiumsilicon oxynitride, tantalum oxide, titanium oxide, barium strontiumtitanium oxide, barium titanium oxide, strontium titanium oxide, yttriumoxide, aluminum oxide, lead scandium tantalum oxide, and lead zincniobate. The high-k materials can further include dopants such aslanthanum and aluminum. In some embodiments of the invention, the high-kdielectric film can have a thickness of about 0.5 nm to about 4 nm. Insome embodiments of the invention, the high-k dielectric film includeshafnium oxide and has a thickness of about 1 nm, although otherthicknesses are within the contemplated scope of the invention.

In some embodiments of the invention, one or more work function layers(not depicted, sometimes referred to as a work function metal stack) areformed between the high-k dielectric film and the bulk gate material.The work function layers can be made of, for example, aluminum,lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide,titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride,molybdenum nitride, niobium nitride, hafnium silicon nitride, titaniumaluminum nitride, tantalum silicon nitride, titanium aluminum carbide,tantalum carbide, and combinations thereof. The work function layer canserve to further modify the work function of the conductive gate 1402and enables tuning of the device threshold voltage. The work functionlayers can be formed to a thickness of about 0.5 to 6 nm, although otherthicknesses are within the contemplated scope of the invention. In someembodiments of the invention, each of the work function layers can beformed to a different thickness. In some embodiments of the invention,the work function layers include a TiN/TiC/TiCA1 stack.

In some embodiments of the invention, a bulk gate material is depositedover the work function layers. The bulk gate material can include anysuitable conducting material, such as, for example, metal (e.g.,tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper,aluminum, lead, platinum, tin, silver, gold), conducting metalliccompound material (e.g., tantalum nitride, titanium nitride, tantalumcarbide, titanium carbide, titanium aluminum carbide, tungsten silicide,tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide),conductive carbon, graphene, or any suitable combination of thesematerials. The conductive material can further include dopants that areincorporated during or after deposition.

In some embodiments of the invention, a gate hard mask 1404 (sometimesreferred to as a Self-Aligned Contact cap, or SAC cap), is formed over asurface of the conductive gate 1402. The gate SAC cap 1404 can be madeof any suitable material, such as, for example, a nitride, siliconnitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. In some embodimentsof the invention, the gate SAC cap 1404 includes silicon nitride. Insome embodiments of the invention, the gate SAC cap 1404 is formed to athickness of 30 nm, although other thicknesses are within thecontemplated scope of the invention.

As depicted in FIG. 14A, the conductive gate 1402 can contact exposedsurfaces of the semiconductor layers 206 and the semiconductor layer602. In this manner, the semiconductor layers 206 and the semiconductorlayer 602 together define a “X-FET” type channel region between the S/Dregions 1202. The channel region includes a vertical fin (e.g., thesemiconductor layer 602) and one or more vertically stacked nanosheets(e.g., the semiconductor layers 206). In some embodiments of theinvention, the conductive gate 1402 is in direct contact(notwithstanding any intervening high-k or work function layers) with asidewall of the vertical fin and a top and bottom surface of each of theone or more nanosheets.

FIGS. 15A and 15B depict cross-sectional views of the “X-FET” typesemiconductor structure 200 during an intermediate operation of a methodof fabricating a semiconductor device according to one or moreembodiments of the invention. As illustrated in FIGS. 15A and 15B,trench contacts 1502 can be formed after removing the dielectric layer1302. The trench contacts 1502 can be formed over the S/D regions 1202using known metallization techniques. In some embodiments of theinvention, the trench contacts 1502 are formed using a self-alignedanisotropic RIE etch whereby the dielectric layer 1302 is etchedselective to the gate SAC Cap 1404 and the spacers 1002. It isunderstood that contacts can be formed over each of the source or drainregions (sometimes referred to as S/D contacts) and over a surface ofthe conductive gate 1402 (sometimes referred to as a gate contact).

The trench contacts 1502 can be of any suitable conducting material,such as, for example, metal (e.g., tungsten, titanium, tantalum,ruthenium, zirconium, cobalt, copper, aluminum, platinum), conductingmetallic compound material (e.g., tantalum nitride, titanium nitride,tantalum carbide, titanium carbide, titanium aluminum carbide, tungstensilicide, tungsten nitride, cobalt silicide, nickel silicide),conductive carbon, or any suitable combination of these materials. Theconductive material can further include dopants that are incorporatedduring or after deposition. In some embodiments of the invention, thecontacts can be copper and can include a barrier metal liner. Thebarrier metal liner prevents the copper from diffusing into, or doping,the surrounding materials, which can degrade their properties. Examplesinclude tantalum nitride and tantalum (TaN/Ta), titanium, titaniumnitride, cobalt, ruthenium, and manganese.

FIGS. 16A-19B depict cross-sectional views of a “GAA X-FET” typesemiconductor structure 1600 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 16A and 16B, apartially fabricated semiconductor device can include a firstsacrificial layer 1602 formed over a substrate 1604.

The first sacrificial layer 1602 and the substrate 1604 can be made of asame material and in a similar manner as the first sacrificial layer 202and the substrate 204, respectively, as depicted in FIG. 2B. In someembodiments of the invention, the germanium concentration in the firstsacrificial layer 1602 is selected to ensure etch selectivity againstany silicon, silicon germanium or germanium layers in the subsequentlyformed gate stack. In some embodiments of the invention, the germaniumconcentration in the first sacrificial layer 1602 is at least 30 percenthigher than any other silicon germanium layers in the stack. In someembodiments of the invention, the first sacrificial layer 1602 caninclude a germanium concentration of 45 to 70 percent, for example 50percent, although other germanium concentrations are within thecontemplated scope of the invention.

In some embodiments of the invention, a stack of one or moresemiconductor layers 1606 alternating with one or more sacrificiallayers 1608 is formed over the first sacrificial layer 1602. The stackcan be formed such that the topmost and bottommost layer of the stackare sacrificial layers. While depicted as a stack having threesemiconductor layers alternating with four sacrificial layers for easeof illustration, it is understood that the stack can include any numberof semiconductor layers alternating with a corresponding number ofsacrificial layers. For example, the stack can include two semiconductorlayers alternating with three sacrificial layers. The semiconductorlayers 1606 and the sacrificial layers 1608 can be made of a samematerial and in a similar manner as the semiconductor layers 206 and thesacrificial layers 208, respectively, as depicted in FIG. 2B.

Each of the semiconductor layers 1606 can have a height ranging from 4nm to 20 nm, for example, from 7 nm to 10 nm. In some embodiments of theinvention, the semiconductor layers 1606 have a height of about 9 nm.The semiconductor layers 1606 can be made of any suitable semiconductorchannel material, such as, for example, monocrystalline Si, III-Vcompound semiconductor, or II-VI compound semiconductor. In someembodiments of the invention, the semiconductor layers 1606 are made ofsilicon.

Each of the sacrificial layers 1608 can have a height ranging from 6 nmto 40 nm, for example, from 8 nm to 20 nm. In some embodiments of theinvention, each of the sacrificial layers 1608 has a same height. Insome embodiments of the invention, some of the sacrificial layers 1608have a different height. For example, in some embodiments of theinvention, the bottommost sacrificial layer has a height of about 10 nm,the topmost sacrificial layer has a height of about 10 nm, and theremaining (e.g., center) sacrificial layers have a height of about 20nm. In some embodiments of the invention, the sacrificial layers 1608are made of silicon germanium. In some embodiments of the invention, thesacrificial layers 1608 include a germanium concentration of 15 to 35percent, for example 25 percent, although other germanium concentrationsare within the contemplated scope of the invention.

FIGS. 17A and 17B depict cross-sectional views of the “GAA X-FET” typesemiconductor structure 1600 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 17A and 17B, a STI1702 is formed over the substrate 1604 to electrically isolate one ormore semiconductor fins. The STI 1702 can be made of a similar materialand formed using a similar process as the STI 304 depicted in FIG. 3A.

In some embodiments of the invention, fin spacers 1704 are formed overthe topmost sacrificial layer of the sacrificial layers 1608 and betweenthe exposed sidewalls of the STI 1702. The fin spacers 1704 can be madeof a similar material and formed using a similar process as the finspacers 402 depicted in FIG. 4A. The fin spacers 1704 can be formed to athickness of about 5 to 10 nm, for example 5 nm, although otherthicknesses are within the contemplated scope of the invention.

In some embodiments of the invention, portions of the semiconductorlayers 1606 and sacrificial layers 1606 that are not covered by the finspacers 1704 are removed to form a trench 1706. In some embodiments ofthe invention, the trench 1706 exposes one or more surfaces of thebottommost sacrificial layer of the sacrificial layers 1608. In someembodiments of the invention, the patterning process can result in arecessing of the bottommost sacrificial layer of the sacrificial layers1608. In some embodiments of the invention, the semiconductor layers1606 and sacrificial layers 1608 are patterned into nanosheets having awidth of 5 nm, although other widths are within the contemplated scopeof the invention.

FIGS. 18A and 18B depict cross-sectional views of the “GAA X-FET” typesemiconductor structure 1600 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 18A and 18B,alternating semiconductor layers 1802 and sacrificial layers 1804 areformed within the trench 1706. In some embodiments of the invention, thesemiconductor layers 1802 and sacrificial layers 1804 are formed using abottom-up trench epitaxy process whereby each layer is successivelyepitaxially grown on the preceding layer within the trench.

The semiconductor layers 1802 and sacrificial layers 1804 can be formedby a variety of methods. In some embodiments of the invention, epitaxialsemiconductor materials can be grown in the trench 1706 using VPE, MBE,LPE, or other suitable processes. The semiconductor layers 1802 can bemade of a similar material as the semiconductor layers 1606. Thesacrificial layers 1804 can be made of a similar material as thesacrificial layers 1608.

In some embodiments of the invention, the height of each of thesemiconductor layers 1802 is the same as the width of each of thecorresponding semiconductor layers 1606. In other words, if thesemiconductor layers 1606 are epitaxially grown to a width of 15 nm, thesemiconductor layers 1802 can be epitaxially grown to a height of 15 nm,although other widths and corresponding thicknesses are within thecontemplated scope of the invention.

FIGS. 19A-19C depict cross-sectional views of the “GAA X-FET” typesemiconductor structure 1600 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. The “GAA X-FET” type semiconductorstructure 1600 can be substantially completed in a similar manner as the“X-FET” type semiconductor structure 200 depicted in FIGS. 2A-15B.

As depicted in FIGS. 19A-19C, the “GAA X-FET” type semiconductorstructure 1600 includes a conductive gate 1902, a SAC cap 1904, S/Dregions 1906, inner spacers 1908, gate spacers 1910, a dielectric layer1912, and contacts 1914. Each of these features can be made of a similarmaterial and by a substantially similar method as the correspondingfeature in the “X-FET” type semiconductor structure 200 depicted inFIGS. 2A-15B.

As depicted in FIG. 19A, the conductive gate 1902 is deposited on theexposed surfaces of the semiconductor layers 1606 and the semiconductorlayers 1802. In this manner, the semiconductor layers 1606 and thesemiconductor layers 1802 together define a “GAA X-FET” type channelregion between the S/D regions 1906. The channel region includes one ormore vertical fins (e.g., the semiconductor layers 1802) and one or morevertically stacked nanosheets (e.g., the semiconductor layers 1606). Insome embodiments of the invention, a high-k dielectric (not depicted) ofthe conductive gate 1902 is in direct contact with a sidewall of thevertical fin and a top and bottom surface of each of the one or morenanosheets.

FIGS. 20-28 depict cross-sectional views of an “X-FET” typesemiconductor structure 2000 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIG. 20, a partiallyfabricated semiconductor device can include a first sacrificial layer2002 formed over a substrate 2004.

The first sacrificial layer 2002 and the substrate 2004 can be made of asame material and in a similar manner as the first sacrificial layer 202and the substrate 204, respectively, as depicted in FIG. 2B. In someembodiments of the invention, a semiconductor layer 2006 is formed overthe first sacrificial layer 2002. The semiconductor layer 2006 can bemade of a same material and in a similar manner as the semiconductorlayer 206 depicted in FIG. 2B. In some embodiments of the invention, thethickness of the semiconductor layer 2006 is greater than the thicknessof the semiconductor layer 206, because the semiconductor layer 2006defines the final thickness (vertical height) of the channel region (asdepicted in FIGS. 29A and 29B). In some embodiments of the invention,the thickness of the semiconductor layer 2006 is about 60 nm, althoughother thicknesses are within the contemplated scope of the invention.

In some embodiments of the invention, a hard mask 2008 can be formed onthe semiconductor layer 2006. In some embodiments of the invention, thehard mask 2008 includes a nitride, such as silicon nitride. In someembodiments of the invention, the hard mask 2008 is formed to athickness of 40 nm, although other thicknesses are within thecontemplated scope of the invention. In some embodiments of theinvention, a second hard mask (not depicted) can be formed on the hardmask 302, to form a bilayer hard mask. In some embodiments of theinvention, the second hard mask includes an oxide, such as, for example,silicon dioxide.

In some embodiments of the invention, portions of the hard mask 2008 areremoved (e.g., patterned) and the semiconductor layer 2006 and firstsacrificial layer 2002 are patterned selective to the hard mask 2008. Asillustrated in FIG. 20, portions of the semiconductor layer 2006 andfirst sacrificial layer 2002 that are not covered by the patterned hardmask 2008 can be removed using a wet etch, a dry etch, or a combinationof sequential wet and/or dry etches.

In some embodiments of the invention, the semiconductor layer 2006 andfirst sacrificial layer 2002 are patterned into one or more fins havinga width ranging from 10 to 50 nm, although other widths are within thecontemplated scope of the invention. For ease of illustration, the stackis depicted as being patterned to form two fins. It is understood,however, that the stack be patterned into any number of parallel fins.In some embodiments of the invention, the pitch, or edge-to-edgespacing, between the fins is about 40 nm, although other spacings arewithin the contemplated scope of the invention.

FIG. 21 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 21, a hard mask 2102 can be formedover a surface of the substrate 2004. The hard mask 2102 can be made ofany suitable material, such as, for example, a low-k dielectric, anitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN. Insome embodiments of the invention, the hard mask 2102 includes siliconnitride. The hard mask 2102 can be formed to a thickness of about 20 to100 nm, for example 70 nm, although other thicknesses are within thecontemplated scope of the invention. In some embodiments of theinvention, the hard mask 2102 is formed to a thickness sufficient tocover sidewalls of the first sacrificial layer 2002.

In some embodiments of the invention, a stack of one or more oxidelayers 2104 alternating with one or more nitride layers 2106 is formedover the hard mask 2102. The stack can be formed such that the topmostand bottommost layer of the stack are oxide layers. While depicted as astack having four oxide layers alternating with three nitride layers forease of illustration, it is understood that the stack can include anynumber of oxide layers alternating with a corresponding number ofnitride layers. For example, the stack can include two oxide layersalternating with a single nitride layer. The number of nitride layers2106 defines the number of fins in the channel region (as depicted inFIG. 25).

Each of the oxide layers 2104 can have a height ranging from 6 nm to 20nm, for example, from 8 nm to 15 nm. In some embodiments of theinvention, the oxide layers 2104 have a height of about 8 nm. The oxidelayers 2104 can be made of any suitable material, such as, for example,silicon oxide.

Each of the nitride layers 2106 can have a height ranging from 4 nm to12 nm, for example, from 7 nm to 10 nm. In some embodiments of theinvention, the nitride layers 2106 have a height of about 9 nm. Thenitride layers 2106 can be made of any suitable material, such as, forexample, silicon nitride.

The oxide layers 2104 and the nitride layers 2106 can be formed byanisotropic deposition. For example, each of the alternating oxide andnitride dielectric materials can be deposited over the hard mask 2102using an HDP deposition plus isotropic etch back process that is cycled(i.e., repeated) “n” times.

FIG. 22 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 22, spacers 2202 are formed overthe topmost oxide layer of the oxide layers 2104 and on exposedsidewalls of the hard mask 2008. In some embodiments of the invention,the spacers 2202 are formed using a conformal deposition process such asCVD, PECVD, UHVCVD, RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, chemicalsolution deposition, or other like processes in combination with a wetor dry etch process. For example, spacer material can be conformallydeposited over the semiconductor structure 2000 and selectively removedusing a RIE to form the side walls spacers 2202. The spacers 2202 can bemade of any suitable material, such as, for example, a low-k dielectric,a nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCN, or SiBCN.In some embodiments of the invention, the spacers 2202 include SiC. Thespacers 2202 can be formed to a thickness of about 5 to 10 nm, forexample 5 nm, although other thicknesses are within the contemplatedscope of the invention.

FIG. 23 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 23, portions of the oxide layers2104, the nitride layers 2106, and the hard mask 2102 can be removed.The oxide layers 2104, the nitride layers 2106, and the hard mask 2102can be removed using a wet etch, a dry etch, or a combination ofsequential wet and/or dry etches. In some embodiments of the invention,the oxide layers 2104, the nitride layers 2106, and the hard mask 2102can be removed using a RIE that stops in the hard mask 2102. In otherwords, the hard mask 2102 can be recessed. In this manner, remainingportions of the hard mask 2102 protect the substrate 2004 duringdownstream processing.

FIG. 24 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 24, the oxide layers 2104 can beremoved to expose a sidewall of the semiconductor layer 2006. The oxidelayers 2104 can be removed using a wet etch or a dry etch. In someembodiments of the invention, the oxide layers 2104 can be removedselective to the nitride layers 2106, the semiconductor layer 2006,and/or the spacers 2202.

FIG. 25 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 25, the semiconductor layer 2006can be recessed laterally to form a recess 2502 exposing a surface ofthe first sacrificial layer 2002 and a surface of the hard mask 2008. Inthis manner, the semiconductor layer 2006 can be recessed to define avertical portion (e.g., a vertical fin) and one or more horizontalportions (e.g., nanosheets). The semiconductor layer 2006 can berecessed using a wet etch or a dry etch. In some embodiments of theinvention, the semiconductor layer 2006 can be recessed selective to thenitride layers 2106 and/or the spacers 2202. In some embodiments of theinvention, remaining portions of the hard mask 2102 protect thesubstrate 2004 from etch back during this process.

FIG. 26 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 26, sacrificial regions 2602 canbe formed in the recess 2502. In some embodiments of the invention, thesacrificial regions 2602 partially fill the recess 2502. In someembodiments of the invention, a sidewall of the sacrificial regions 2602is coplanar to a sidewall of the hard mask 2008.

In some embodiments of the invention, the sacrificial regions 2602 aremade of silicon germanium. In some embodiments of the invention, thesacrificial regions 2602 include a germanium concentration of 15 to 45percent, for example 25 percent, although other germanium concentrationsare within the contemplated scope of the invention. In some embodimentsof the invention, the sacrificial regions 2602 are epitaxially grown onexpose surfaces of the semiconductor layer 2006. In some embodiments ofthe invention, remaining portions of the hard mask 2102 protect thesubstrate 2004 parasitic epitaxial growth during this process.

FIG. 27 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. As depicted in FIG. 27, the spacers 2202, the nitridelayers 2106, and the hard mask 2102 can be removed. The spacers 2202,the nitride layers 2106, and the hard mask 2102 can be removed using awet etch, a dry etch, or a combination of sequential wet and/or dryetches. In some embodiments of the invention, the spacers 2202, thenitride layers 2106, and the hard mask 2102 can be removed using a RIEor a nitride stripping process.

In some embodiments of the invention, a STI 2702 is formed over thesubstrate 2004 to electrically isolate one or more semiconductor fins.The STI 2702 can be any suitable dielectric material, such as, forexample, a silicon oxide, and can be formed using any suitable process.The STI 2702 can be formed using, for example, CVD, FVCD, PECVD, UHVCVD,RTCVD, MOCVD, LPCVD, LRPCVD, ALD, PVD, HDP, chemical solutiondeposition, spin-on dielectrics, or other like processes. In someembodiments of the present invention, the STI 2702 is overfilled andthen recessed using, for example, a chemical-mechanical planarization(CMP) process.

In some embodiments of the invention, the STI 2702 is recessed below asurface of the first sacrificial layer 2002. In this manner, the STI2702 electrically isolates one or more nanosheets stacks. The STI 2702can be recessed using, for example, chemical oxide removal (COR) orhydrofluoric acid (HF) wet etch. In some embodiments of the invention,the STI 2702 is recessed selective to the hard mask 2008.

FIG. 28 depicts a cross-sectional view of the “X-FET” type semiconductorstructure 2000 during an intermediate operation of a method offabricating a semiconductor device according to one or more embodimentsof the invention. The “X-FET” type semiconductor structure 2000 can besubstantially completed in a similar manner as the “X-FET” typesemiconductor structure 200 depicted in FIGS. 2A-15B.

As depicted in FIG. 28, the “X-FET” type semiconductor structure 2000includes a conductive gate 2802 and a gate hard mask 2804. In someembodiments of the invention, the semiconductor structure 2000 furtherincludes S/D regions, inner spacers, gate spacers, a dielectric layer,and contacts (not depicted). Each of these features can be made of asimilar material and by a substantially similar method as thecorresponding feature in the “X-FET” type semiconductor structure 200depicted in FIGS. 2A-15B.

As depicted in FIG. 28, the conductive gate 2802 can be deposited overexposed surfaces of the semiconductor layer 2006. In this manner, thevertical portion (e.g., vertical fin) and horizontal portions (e.g.,nanosheets) of the semiconductor layer 2006 define a “X-FET” typechannel region between the S/D regions. In some embodiments of theinvention, high-k dielectric layers of the conductive gate 2802 are indirect contact with a sidewall of the vertical fin and a top and bottomsurface of each of the one or more nanosheets.

FIGS. 29A-31B depict cross-sectional views of a “X-FET” typesemiconductor structure 2900 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 29A and 29B, apartially fabricated semiconductor device can include a buried oxide(BOX) layer 2902 formed over a substrate 2904. The BOX layer 2902 can beformed using known silicon-on-insulator (SOI) processes, and caninclude, for example, silicon dioxide or sapphire. The substrate 1604can be made of a same material and in a similar manner as the substrate204, as depicted in FIG. 2B.

In some embodiments of the invention, a stack of one or more firstsemiconductor layers 2906 alternating with one or more secondsemiconductor layers 2908 is formed over the BOX layer 2902. Whiledepicted as a stack having three first semiconductor layers 2906alternating with four second semiconductor layers 2908 for ease ofillustration, it is understood that the stack can include any number offirst semiconductor layers alternating with a corresponding number ofsecond semiconductor layers. The first semiconductor layers 2906 and thesecond semiconductor layers 2908 can be formed in a similar manner asthe semiconductor layers 206 and the sacrificial layers 208,respectively, as depicted in FIG. 2B. In some embodiments of theinvention, the first semiconductor layers 2906 are made of silicon whilethe second semiconductor layers 2908 are made of silicon germanium.

Each of the first semiconductor layers 2906 can have a height rangingfrom 4 nm to 12 nm, for example, from 7 nm to 10 nm. In some embodimentsof the invention, the first semiconductor layers 2906 have a height ofabout 8 nm. Each of the second semiconductor layers 2908 can have aheight ranging from 6 nm to 40 nm, for example, from 8 nm to 20 nm. Insome embodiments of the invention, each of the second semiconductorlayers 2908 has a same height as the first semiconductor layers 2906. Insome embodiments of the invention, the second semiconductor layers 2908include a germanium concentration of 15 to 35 percent, for example 25percent, although other germanium concentrations are within thecontemplated scope of the invention.

In some embodiments of the invention, a hard mask 2910 can be formed onthe topmost layer of the second semiconductor layers 2908. In someembodiments of the invention, the hard mask 2910 includes a nitride,such as silicon nitride. In some embodiments of the invention, the hardmask 2910 is formed to a thickness of 40 nm, although other thicknessesare within the contemplated scope of the invention. In some embodimentsof the invention, a second hard mask (not depicted) can be formed on thehard mask 2910, to form a bilayer hard mask. In some embodiments of theinvention, the second hard mask includes an oxide, such as, for example,silicon dioxide.

In some embodiments of the invention, portions of the hard mask 2910 areremoved (e.g., patterned) and the stack of first semiconductor layers2906 and second semiconductor layers 2908 is patterned selective to thehard mask 2910. Portions of the first semiconductor layers 2906 and thesecond semiconductor layers 2908 that are not covered by the patternedhard mask 2910 can be removed using a wet etch, a dry etch, or acombination of sequential wet and/or dry etches.

FIGS. 30A and 30B depict cross-sectional views of the “X-FET” typesemiconductor structure 2900 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 30A and 30B, thesecond semiconductor layers 2908 are recessed to form one or morerecesses 3002.

In some embodiments of the invention, the second semiconductor layers2908 are recessed selective to the first semiconductor layers 2906. Thesecond semiconductor layers 2908 can be recessed using any suitableprocess capable of removing a silicon germanium layer selective to asilicon layer or a silicon germanium layer having a lower germaniumconcentration. Example processes known to provide this etch selectivityinclude hydrophosphoric acid, HC1 vapor phase chemistries and chlorinetrifluoride (ClF₃) etches.

FIGS. 31A and 31B depict cross-sectional views of the “X-FET” typesemiconductor structure 2900 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 31A and 31B, thesemiconductor structure 2900 is subjected to an annealing processwhereby the germanium in the second semiconductor layers 2908 diffusesuniformly throughout the first semiconductor layers 2906 and the secondsemiconductor layers 2908.

The resulting semiconductor layers 3102 include silicon germanium havinga germanium concentration that is between 0 and the pre-anneal germaniumconcentration of the second semiconductor layers 2908. For example, ifthe second semiconductor layers 2908 was SiGe 20% (e.g., 20% Ge), thefinal germanium concentration in the semiconductor layers 3102 will beless than 20%. In some embodiments of the invention, the semiconductorstructure 2900 can be annealed at a temperature of about 950 to 1150degrees Celsius.

In some embodiments of the invention, the “X-FET” type semiconductorstructure 2900 can be substantially completed in a similar manner as the“X-FET” type semiconductor structure 200 depicted in FIGS. 2A-15B. The“X-FET” type semiconductor structure 2900 can include a conductive gate,a gate SAC Cap, S/D regions, inner spacers, gate spacers, a dielectriclayer, and contacts (not depicted). Each of these features can be madeof a similar material and by a substantially similar method as thecorresponding feature in the “X-FET” type semiconductor structure 200depicted in FIGS. 2A-15B.

FIGS. 32A-35B depict cross-sectional views of a “junction-less X-FET”type semiconductor structure 3200 during an intermediate operation of amethod of fabricating a semiconductor device according to one or moreembodiments of the invention. As depicted in FIGS. 32A and 32B, apartially fabricated semiconductor device can include a BOX layer 3202formed over a substrate 3204. The BOX layer 3202 and the substrate 3204can be made of a same material and in a similar manner as the BOX layer2902 and the substrate 2904, respectively, as depicted in FIG. 29A.

In some embodiments of the invention, a stack of one or more firstsemiconductor layers 3206 alternating with one or more secondsemiconductor layers 3208 is formed over the BOX layer 3202. Whiledepicted as a stack having three first semiconductor layers 3206alternating with four second semiconductor layers 3208 for ease ofillustration, it is understood that the stack can include any number offirst semiconductor layers alternating with a corresponding number ofsecond semiconductor layers. In some embodiments of the invention, thefirst semiconductor layers 3206 are made of silicon while the secondsemiconductor layers 3208 are made of doped silicon, such as, forexample, boron-doped silicon.

The second semiconductor layers 3208 can be doped using in-situ dopedepitaxy, doped following the epitaxy, or by implantation and plasmadoping. In some embodiments of the invention, the first semiconductorlayers 3206 and the second semiconductor layers 3208 are formed using anepitaxy process whereby each layer is successively epitaxially grown onthe preceding layer.

Each of the first semiconductor layers 3206 can have a height rangingfrom 4 nm to 12 nm, for example, from 7 nm to 10 nm. In some embodimentsof the invention, the first semiconductor layers 3206 have a height ofabout 8 nm. Each of the second semiconductor layers 3208 can have aheight ranging from 6 nm to 40 nm, for example, from 8 nm to 20 nm. Insome embodiments of the invention, each of the second semiconductorlayers 3208 has a same height as the first semiconductor layers 3206. Insome embodiments of the invention, the second semiconductor layers 3208include a boron dopant concentration ranging from 10¹³ cm⁻³ to 10¹⁸cm⁻³, although other boron dopant concentrations are within thecontemplated scope of the invention.

In some embodiments of the invention, a hard mask 3210 can be formed onthe topmost layer of the second semiconductor layers 3208. In someembodiments of the invention, the hard mask 3210 includes a nitride,such as silicon nitride. In some embodiments of the invention, the hardmask 3210 is formed to a thickness of 40 nm, although other thicknessesare within the contemplated scope of the invention. In some embodimentsof the invention, a second hard mask (not depicted) can be formed on thehard mask 3210, to form a bilayer hard mask. In some embodiments of theinvention, the second hard mask includes an oxide, such as, for example,silicon dioxide.

In some embodiments of the invention, portions of the hard mask 3210 areremoved (e.g., patterned) and the stack of first semiconductor layers3206 and second semiconductor layers 3208 is patterned selective to thehard mask 3210. Portions of the first semiconductor layers 3206 and thesecond semiconductor layers 3208 that are not covered by the patternedhard mask 3210 can be removed using a wet etch, a dry etch, or acombination of sequential wet and/or dry etches.

FIGS. 33A and 33B depict cross-sectional views of the “junction-lessX-FET” type semiconductor structure 3200 during an intermediateoperation of a method of fabricating a semiconductor device according toone or more embodiments of the invention. As depicted in FIGS. 33A and33B, the second semiconductor layers 3208 are recessed to form one ormore recesses 3302.

In some embodiments of the invention, the second semiconductor layers3208 are recessed selective to the first semiconductor layers 3206. Thesecond semiconductor layers 3208 can be recessed using any suitableprocess capable of removing a doped silicon layer (e.g., a boron-dopedsilicon) selective to a silicon layer. Example processes known toprovide this etch selectivity include ammonia-based chemistries andtetramethylammonium hydroxide (TMAH or TMAOH) etches.

FIGS. 34A and 34B depict cross-sectional views of the “junction-lessX-FET” type semiconductor structure 3200 during an intermediateoperation of a method of fabricating a semiconductor device according toone or more embodiments of the invention. As depicted in FIGS. 34A and34B, the semiconductor structure 3200 is subjected to an annealingprocess whereby the dopants (e.g., boron) in the second semiconductorlayers 3208 diffuse uniformly throughout the first semiconductor layers3206 and the second semiconductor layers 3208.

The resulting semiconductor layers 3402 include doped silicon having adopant concentration that is between 0 and the pre-anneal dopantconcentration of the second semiconductor layers 3208. For example, ifthe second semiconductor layers 2908 was boron doped silicon having aboron concentration of 10¹⁵ cm⁻³, the final boron dopant concentrationin the semiconductor layers 3402 will be less than 10¹⁵ cm⁻³. In someembodiments of the invention, the semiconductor structure 3200 can beannealed at a temperature of about 950 to 1150 degrees Celsius. At thispoint, the semiconductor structure 3200 is a junction-less device(sometimes referred to as a junction-free device).

FIGS. 35A and 35B depict cross-sectional views of the “junction-lessX-FET” type semiconductor structure 3200 during an intermediateoperation of a method of fabricating a semiconductor device according toone or more embodiments of the invention. As depicted in FIGS. 35A and35B, the intrinsic silicon channels in the semiconductor structure 3200can be recovered if a junction-less device is not desired. In someembodiments of the invention, the semiconductor structure 3200 issubjected to a hydrogen treatment to pump out the dopants (e.g., boron)within the semiconductor layers 3402.

In some embodiments of the invention, several “junction-less X-FET” typesemiconductor structure are formed, and only a subset of thosestructures are subjected to the hydrogen treatment (using, e.g., maskingor other isolation techniques). In this manner, some “junction-lessX-FET” type semiconductor structures can be formed along sideconventional semiconductor structures having active junctions.

In some embodiments of the invention, the “junction-less X-FET” typesemiconductor structure 3200 (or conventional structure following ahydrogen treatment) can be substantially completed in a similar manneras the “X-FET” type semiconductor structure 200 depicted in FIGS.2A-15B. The “junction-less X-FET” type semiconductor structure 3200 caninclude a conductive gate, a SAC cap, S/D regions, inner spacers, gatespacers, a dielectric layer, and contacts (not depicted). Each of thesefeatures can be made of a similar material and by a substantiallysimilar method as the corresponding feature in the “X-FET” typesemiconductor structure 200 depicted in FIGS. 2A-15B.

FIG. 36 depicts a flow diagram 3600 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. The semiconductor device can include a non-planar channelregion having a first semiconductor layer, a second semiconductor layer,and a fin-shaped bridge layer between the first semiconductor layer andthe second semiconductor layer (e.g., as depicted in FIGS. 15A and 15B).Outer surfaces of the first semiconductor layer, the secondsemiconductor layer, and the fin-shaped bridge region define aneffective channel width of the non-planar channel region. In someembodiments of the invention, a width of the first semiconductor layeris greater than a width of the fin-shaped bridge region. In someembodiments of the invention, a width of the second semiconductor layeris greater than a width of the fin-shaped bridge region. In someembodiments of the invention, a width of the first semiconductor layeris the same as a width of the second semiconductor layer.

As shown at block 3602, a first sacrificial layer is formed on asubstrate. As shown at block 3604, a nanosheet stack is formed on thefirst sacrificial layer. The nanosheet stack includes a firstsemiconductor layer and a second sacrificial layer.

At block 3606 a first fin spacer is formed on a first portion of thenanosheet stack. At block 3608 a second fin spacer is formed on a secondportion of the nanosheet stack. As shown at block 3610, a trench isformed by removing a third portion of the nanosheet stack. The trenchexposes a surface of the first sacrificial layer. At block 3612 a secondsemiconductor layer is formed in the trench on the surface of the firstsacrificial layer.

FIG. 37 depicts a flow diagram 3700 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 3702, a semiconductor layer is formed on asubstrate. At block 3704, a stack of alternating oxide layers andnitride layers are formed adjacent to the semiconductor layer.

As shown at block 3706, the oxide layers are removed to expose asidewall of the semiconductor layer. At block 3708 the exposed sidewallof the semiconductor layer is recessed to define a vertical portion andone or more horizontal portions of the semiconductor layer.

FIG. 38 depicts a flow diagram 3800 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 3802, a nanosheet stack is formed over asubstrate. The nanosheet stack includes a first semiconductor layer anda second semiconductor layer. The second semiconductor layer includes afirst material.

At block 3804 a sidewall of the second semiconductor layer is recessed.At block 3806 the structure is annealed at a temperature operable touniformly diffuse the first material through the first semiconductorlayer and the second semiconductor layer.

FIG. 39 depicts a flow diagram 3900 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 3902, a stack of alternating semiconductorlayers and doped semiconductor layers is formed over a substrate. Thedoped semiconductor layers include a dopant.

As shown in block 3904, a sidewall of the doped semiconductor layers isrecessed. At block 3906 the structure is annealed at a temperatureoperable to uniformly diffuse the dopant through the semiconductorlayers and the doped semiconductor layers.

FIG. 40 depicts a flow diagram 4000 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 4002, a nanosheet stack is formed over asubstrate. The nanosheet stack includes one or more first semiconductorlayers and one or more first sacrificial layers.

As shown in block 4004, a trench is formed by removing a portion of theone or more first semiconductor layers and the one or more firstsacrificial layers. The trench exposes a surface of a bottommostsacrificial layer of the one or more first sacrificial layers. At block4006 the trench is filled with one or more second semiconductor layersand one or more second sacrificial layers such that each of the one ormore second semiconductor layers is in contact with a sidewall of one ofthe one or more first semiconductor layers.

FIG. 41 depicts a flow diagram 4100 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 4102, a first channel region is formed overa substrate. The first channel region includes a first vertical fin anda first nanosheet extending from a sidewall of the first vertical fin.

As shown in block 4104, a second channel region is formed over the firstchannel region. The second channel region includes a second vertical finand a second nanosheet extending from a sidewall of the second verticalfin. At block 4106 a gate is formed over the first channel region andthe second channel region. The gate in contact with a topmost surface ofthe first channel region and a bottommost surface of the second channelregion.

The methods and resulting structures described herein can be used in thefabrication of IC chips. The resulting IC chips can be distributed bythe fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includes ICchips, ranging from toys and other low-end applications to advancedcomputer products having a display, a keyboard or other input device,and a central processor.

Various embodiments of the present invention are described herein withreference to the related drawings. Alternative embodiments can bedevised without departing from the scope of this invention. Althoughvarious connections and positional relationships (e.g., over, below,adjacent, etc.) are set forth between elements in the followingdescription and in the drawings, persons skilled in the art willrecognize that many of the positional relationships described herein areorientation-independent when the described functionality is maintainedeven though the orientation is changed. These connections and/orpositional relationships, unless specified otherwise, can be direct orindirect, and the present invention is not intended to be limiting inthis respect. Similarly, the term “coupled” and variations thereofdescribes having a communications path between two elements and does notimply a direct connection between the elements with no interveningelements/connections between them. All of these variations areconsidered a part of the specification. Accordingly, a coupling ofentities can refer to either a direct or an indirect coupling, and apositional relationship between entities can be a direct or indirectpositional relationship. As an example of an indirect positionalrelationship, references in the present description to forming layer “A”over layer “B” include situations in which one or more intermediatelayers (e.g., layer “C”) is between layer “A” and layer “B” as long asthe relevant characteristics and functionalities of layer “A” and layer“B” are not substantially changed by the intermediate layer(s).

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as anexample, instance or illustration.” Any embodiment or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” are understood to include any integer number greaterthan or equal to one, i.e. one, two, three, four, etc. The terms “aplurality” are understood to include any integer number greater than orequal to two, i.e. two, three, four, five, etc. The term “connection”can include an indirect “connection” and a direct “connection.”

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedcan include a particular feature, structure, or characteristic, butevery embodiment may or may not include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper,” “lower,”“right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” andderivatives thereof shall relate to the described structures andmethods, as oriented in the drawing figures. The terms “overlying,”“atop,” “on top,” “positioned on” or “positioned atop” mean that a firstelement, such as a first structure, is present on a second element, suchas a second structure, wherein intervening elements such as an interfacestructure can be present between the first element and the secondelement. The term “direct contact” means that a first element, such as afirst structure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,”“upper,” and the like, are used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device can be otherwise oriented (e.g., rotated 90degrees or at other orientations), and the spatially relativedescriptors used herein should be interpreted accordingly.

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

The phrase “selective to,” such as, for example, “a first elementselective to a second element,” means that the first element can beetched and the second element can act as an etch stop.

The term “conformal” (e.g., a conformal layer) means that the thicknessof the layer is substantially the same on all surfaces, or that thethickness variation is less than 15% of the nominal thickness of thelayer.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases can be controlled and the systemparameters can be set so that the depositing atoms arrive at thedeposition surface of the semiconductor substrate with sufficient energyto move about on the surface such that the depositing atoms orientthemselves to the crystal arrangement of the atoms of the depositionsurface. An epitaxially grown semiconductor material can havesubstantially the same crystalline characteristics as the depositionsurface on which the epitaxially grown material is formed. For example,an epitaxially grown semiconductor material deposited on a {100}orientated crystalline surface can take on a {100} orientation. In someembodiments of the invention of the invention, epitaxial growth and/ordeposition processes can be selective to forming on semiconductorsurface, and may or may not deposit material on exposed surfaces, suchas silicon dioxide or silicon nitride surfaces.

As previously noted herein, for the sake of brevity, conventionaltechniques related to semiconductor device and integrated circuit (IC)fabrication may or may not be described in detail herein. By way ofbackground, however, a more general description of the semiconductordevice fabrication processes that can be utilized in implementing one ormore embodiments of the present invention have been provided. Althoughspecific fabrication operations used in implementing one or moreembodiments of the present invention can be individually known, thedescribed combination of operations and/or resulting structures of thepresent invention are unique. Thus, the unique combination of theoperations described in connection with the fabrication of asemiconductor device according to the present invention utilize avariety of individually known physical and chemical processes performedon a semiconductor (e.g., silicon) substrate, some of which aredescribed in the immediately following paragraphs.

In general, the various processes used to form a micro-chip that will bepackaged into an IC fall into four general categories, namely, filmdeposition, removal/etching, semiconductor doping andpatterning/lithography. Deposition is any process that grows, coats, orotherwise transfers a material onto the wafer. Available technologiesinclude physical vapor deposition (PVD), chemical vapor deposition(CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE)and more recently, atomic layer deposition (ALD) among others.Removal/etching is any process that removes material from the wafer.Examples include etch processes (either wet or dry), chemical-mechanicalplanarization (CMP), and the like. Reactive ion etching (ME), forexample, is a type of dry etching that uses chemically reactive plasmato remove a material, such as a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions thatdislodge portions of the material from the exposed surface. The plasmais typically generated under low pressure (vacuum) by an electromagneticfield. Semiconductor doping is the modification of electrical propertiesby doping, for example, transistor sources and drains, generally bydiffusion and/or by ion implantation. These doping processes arefollowed by furnace annealing or by rapid thermal annealing (RTA).Annealing serves to activate the implanted dopants. Films of bothconductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators(e.g., various forms of silicon dioxide, silicon nitride, etc.) are usedto connect and isolate transistors and their components. Selectivedoping of various regions of the semiconductor substrate allows theconductivity of the substrate to be changed with the application ofvoltage. By creating structures of these various components, millions oftransistors can be built and wired together to form the complexcircuitry of a modern microelectronic device. Semiconductor lithographyis the formation of three-dimensional relief images or patterns on thesemiconductor substrate for subsequent transfer of the pattern to thesubstrate. In semiconductor lithography, the patterns are formed by alight sensitive polymer called a photo-resist. To build the complexstructures that make up a transistor and the many wires that connect themillions of transistors of a circuit, lithography and etch patterntransfer steps are repeated multiple times. Each pattern being printedon the wafer is aligned to the previously formed patterns and slowly theconductors, insulators and selectively doped regions are built up toform the final device.

The flowchart and block diagrams in the Figures illustrate possibleimplementations of fabrication and/or operation methods according tovarious embodiments of the present invention. Variousfunctions/operations of the method are represented in the flow diagramby blocks. In some alternative implementations, the functions noted inthe blocks can occur out of the order noted in the Figures. For example,two blocks shown in succession can, in fact, be executed substantiallyconcurrently, or the blocks can sometimes be executed in the reverseorder, depending upon the functionality involved.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments described. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

What is claimed is:
 1. A method for forming a semiconductor device, themethod comprising: forming a nanosheet stack over a substrate, thenanosheet stack comprising one or more first semiconductor layers andone or more first sacrificial layers; forming a trench by removing aportion of the one or more first semiconductor layers and the one ormore first sacrificial layers, the trench exposing a surface of abottommost sacrificial layer of the one or more first sacrificiallayers; and filling the trench with one or more second semiconductorlayers and one or more second sacrificial layers such that each of theone or more second semiconductor layers is in contact with a sidewall ofone of the one or more first semiconductor layers.
 2. The method ofclaim 1, wherein the one or more first semiconductor layers comprisesilicon and the one or more first sacrificial layers comprise silicongermanium.
 3. The method of claim 2 further comprising forming a thirdsacrificial layer between the bottommost sacrificial layer.
 4. Themethod of claim 3, wherein the third sacrificial layer comprises silicongermanium having a higher germanium concentration than the bottommostsacrificial layer.
 5. The method of claim 1, wherein the one or morefirst semiconductor layers each comprise a height of about 8 nm.
 6. Themethod of claim 1, wherein the bottommost sacrificial layer and atopmost sacrificial layer of the one or more first sacrificial layerscomprise a height of about 10 nm and the remaining sacrificial layers ofthe one or more first semiconductor layers each comprise a height ofabout 20 nm.
 7. The method of claim 1, wherein the trench comprises awidth of about 5 nm.
 8. The method of claim 3 further comprising forminga shallow trench isolation adjacent to the nanosheet stack.
 9. Themethod of claim 8 further comprising recessing the shallow trenchisolation below a surface of the third sacrificial layer.
 10. The methodof claim 3 further comprising removing the third sacrificial layerselective to the one or more first sacrificial layers and the one ormore second sacrificial layers to define a cavity.
 11. The method ofclaim 10 further comprising filling the cavity with a bottom spacer. 12.The method of claim 1 further comprising removing the one or more firstsacrificial layers and the one or more second sacrificial layers. 13.The method of claim 1 further comprising forming a gate over thenanosheet stack.
 14. A method for forming a semiconductor device, themethod comprising: forming a first channel region over a substrate, thefirst channel region comprising a first vertical fin and a firstnanosheet extending from a sidewall of the first vertical fin; forming asecond channel region over the first channel region, the second channelregion comprising a second vertical fin and a second nanosheet extendingfrom a sidewall of the second vertical fin; and forming a gate over thefirst channel region and the second channel region, the gate in contactwith a topmost surface of the first channel region and a bottommostsurface of the second channel region.
 15. The method of claim 14 furthercomprising forming a bottom spacer between the first channel region andthe substrate.
 16. A semiconductor device comprising: a first channelregion over a substrate, the first channel region comprising a firstvertical fin and a first nanosheet extending from a sidewall of thefirst vertical fin; a second channel region over the first channelregion, the second channel region comprising a second vertical fin and asecond nanosheet extending from a sidewall of the second vertical fin;and a gate over the first channel region and the second channel region,the gate in contact with a topmost surface of the first channel regionand a bottommost surface of the second channel region.
 17. Thesemiconductor device of claim 16 further comprising a bottom spacerbetween the first channel region and the substrate.
 18. Thesemiconductor device of claim 16 further comprising an inner spacerbetween the first channel region and the second channel region.
 19. Thesemiconductor device of claim 16 further comprising: a source adjacentto a first sidewall of the first channel region; and a drain adjacent toa second sidewall of the first channel region.
 20. The semiconductordevice of claim 16 further comprising a third channel region over thesecond channel, the third channel region comprising a third vertical finand a third nanosheet extending from a sidewall of the third verticalfin.